1. Field of the Invention
The present invention relates to an apparatus and method for data check for a storage system, e.g., a disk array system which is provided with a plurality of magnetic disk drives and which operates these magnetic disk drives in parallel and which allows data to be simultaneously input to these magnetic disk drives and to be output therefrom.
There is recently a tendency to demand, in a computer system, a transfer of large amounts of data at high speed, and therefore, an auxiliary storage system is also required to transfer large amounts of data at high speed to exchange data with a host device.
To meet this requirement, the auxiliary storage system, e.g., magnetic disk array system, has been developed, which is mainly constituted from a plurality of storage devices such as several units of magnetic disk drives and which enables plural bytes of data to be transferred in parallel between the host device and the storage devices.
2. Description of the Related Art
Here, the conventional magnetic disk array system, which is representative of the storage system, will be explained more specifically.
In general, in a single unit of a magnetic disk drive, data transfer speed is limited by a rotation speed of a motor which rotates a magnetic disk as a recording medium. Accordingly, if it is intended to attain high speed operation by increasing a data transfer speed, it is necessary to perform write/read operations in parallel by driving a plurality of disk drives simultaneously. At this time, according to a command from a host device, the spindle motors of the magnetic disk drives connected in parallel with the host device are synchronously rotated, so that it becomes possible to perform a parallel transfer of data. Such a construction is called a disk array system, or a disk array device.
Further, in addition to the data transfer at high speed, fault tolerance of the whole system is also required for such a disk array system so that sufficient reliability for the large amounts of data can be ensured without decreasing the data transfer speed.
To attain such a fault tolerant system, even though a failure, such as the inability to read data from one disk drive of a plurality of disk drives, has occurred, it is necessary for the disk array system to be constructed so that the data of the failed disk drive can be reconstructed immediately without stopping operation of the whole disk array system.
Some kinds of disk array systems in practical use, in which the above-mentioned data transfer at high speed and the fault tolerance can be satisfied simultaneously, have begun to be announced by various computer manufacturers as the products of disk array system called RAID (Redundant Arrays of Inexpensive Disks) 1 to RAID 5.
Among these RAIDs 1-5, RAID 3, which is especially adequate for the case where large amounts of data have to be processed continuously at high speed, e.g., scientific calculations, will be described in more detail.
In the RAID 3, the disk array system typically includes a plurality of disk drives for data transfer (for example, eight (8) disk drives) and a disk drive for parity checking, all these disk drives operating in parallel simultaneously. In this case, some given parity data corresponding to the parallel data of the respective disk drives for data transfer are previously stored in the disk drive for parity checking (parity disk drive). In such a construction, even though one disk drive of a plurality of disk drives fails so that the data cannot be read out, the data can be reconstructed by reading the parity data from the parity disk drive.
Further, in the RAID 3, a spare storage disk drive is also provided. All the data in the failed disk drive is automatically reconstructed and transferred into the spare storage disk drive. If the reconstruction process is completed, the spare storage device can be utilized as a normal disk drive, in cooperation with the other disk drives for data transfer.
In this manner, the disk array system as represented by the RAID 3, which enables large amounts of data to be transferred at relatively high speed (for example, 36 M Bytes/sec) and has substantially fault tolerant characteristics, can be prepared.
Further, when such large amounts of data are actually transferred into a plurality of disk drives in parallel and are written therein simultaneously, it is necessary to examine whether or not all the written data are correct, so that the reliability of the above-mentioned large amounts of written data can be ensured as highly as that of small amounts of data.
In this case, it is desirable that some measures for confirming the write data in a simple manner and in a relatively short time should be taken, in order to maintain the data reliability without remarkably decreasing data transfer speed.
As a typical one of these measures, a method of adding an error detecting code such as CRC (cyclic redundancy check) data, for each data block of a certain byte length, is in practical use.
Hereinafter, a conventional apparatus and method for data checking executed by adding CRC data will be described with reference to FIGS. 1 to 3, so that a process of data checking for a disk array system will be understood more clearly.
FIGS. 1 to 3 are block diagrams for explaining a process of data checking according to a prior art. To be more specific, FIG. 1 is a block diagram of a disk array system, FIG. 2 is a block diagram for explaining a CRC adding process, and FIG. 3 is a block diagram of a data path control circuit.
In these figures, 31 denotes a host computer (HOST), 32 a disk array system, 33 a disk controller, 34 storage devices (e.g., magnetic disk drives), and 35 a data path control circuit. Especially, in FIG. 3, 36, 37, 44 and 45 denote register units, respectively, and 38 denotes a host CRC checker, 39 a host CRC generator, 40 a write data converter, 41 a device CRC generator, 42 a read data converter, and 43 a device CRC checker.
A currently used disk array system is constructed, for example, as shown in FIG. 3. As illustrated in FIG. 3, the disk array system 32 is provided with a disk controller 33 and a plurality of storage devices 34, e.g., a plurality of magnetic disk drives.
This disk array system 32 is connected to a host device, e.g., a host computer (HOST) 31 and is used as a subsystem (which is so-called DIA: Disk In Array) for the host computer 31.
Among the plurality of storage devices 34, typically, eight storage devices (DV0 to DV7) are used for storing normal data, one storage device (DVP) is used for storing parity data, and one storage device (DVS) is used as a spare storage device.
The disk array system 32 realizes data transfer at high speed by operating the plurality of storage devices 34 in parallel, and by inputting and outputting data to and from these storage devices 34 simultaneously.
The disk array system 32 also operates the parity storage device (DVP) in parallel independently of the storage devices (e.g., DV0 to DV7) for storing the data, thereby storing parity data in this storage device (DVP).
With this arrangement, even if one of the eight storage devices (DV0 to DV7) for storing the data becomes unable to read data, the data can be reconstructed from the parity storage device (DVP).
Further, when a failure has occurred in one of the eight storage devices (DV0 to DV7), the data stored in the failed storage device is transferred to the spare storage device (DVS), and thereafter the spare storage device can be used for normal operation.
In the disk array system 32, data blocks from the host computer 31 is divided and written in the plurality of storage devices 34. At this time, typically, CRC data is added as an error detecting code to each of the divided data blocks (normally data to be stored in one sector) including a specified number of bytes of data from the disk controller 33, and is written in each of the storage devices 34 together with the data, thereby securing the data.
The CRC data adding process is illustrated in FIG. 2. In this case, it is assumed that the data transmitted through four paths from the host computer 31 (hereinafter referred to as four path data) is converted by the data path control circuit 35 provided in the disk controller 33 so as to be transferred to the storage devices through eight paths (hereinafter referred to as eight path data).
In this way, the four path data are converted into the eight path data, which are written in the plurality of storage devices (DV0 to DV7). At this time, the CRC data are generated from each data transferred through the paths from the host computer 31.
For instance, in the case of a host CRCH0 (CRC data added in the host computer 31), it is generated from data DT0, DT4, DT8, DT12, DT16, DT20, etc.
Further, a host CRCH1 is generated from DT1, DT5, DT9, DT13, DT17, DT21, etc., and a host CRCH2 is generated from DT2, DT6, DT10, DT14, DT18, DT22, etc.
Device CRCs (CRC data added to the data to be read from the storage devices in the data path control circuit) are generated for each of the eight divided paths. For instance, a CRCD0 is generated from DT0, DT8, DT16, etc. Further, a CRCD1 is generated from DT1, DT9, DT17, etc., and a CRCD2 is generated from DT2, DT10, DT18, etc.
An exemplary data path control circuit 35 will be described with reference to FIG. 3.
As shown in FIG. 3, the data path control circuit 35 is provided with register units (REG) 36, 37, 44 and 45, a host CRC checker (HOST CRC CHK) 38, a host CRC generator (HOST CRC GEN) 39, a write data converter 40, a read data converter 42, and the like.
Further, the write data converter 40 includes a device CRC generator (DV CRC GEN) 41, and the read data converter 42 includes a device CRC checker (DV CRC CHK) 43.
The register unit 36 is used when the write data are input to the data path control circuit 35, and the register unit 36 includes registers WI0 to WI3 corresponding to the four paths. The register unit 37 is used when the read data are output from the data path control circuit 35, and the register unit 37 includes registers RO0 to R03 corresponding to the four paths.
The register unit 44 is used when the write data are output from the write data converter 40, and the register unit 44 includes registers WO0 to WO7 for storing normal data, a parity register WOP for storing a parity data, and a spare register WOS.
The register unit 45 is used when the read data are input to the read data converter 45, and the register unit 45 includes registers RI0 to RI7 for storing the normal data, a parity register RIP for storing a parity data, and a spare register RIS.
During the transfer of the write data, the data transmitted to the four paths from the host computer 31 are temporarily stored in the register unit 36. Thereafter, the data are converted from four path data into eight path data by the write data converter 40 after the CRC data are checked by the host CRC checker 38.
As this time, the CRC data are added to the data for the respective paths by the device CRC generator 41, and the eight path data and the parity data are temporarily stored in the register unit 44. Thereafter, the data are transferred to the respective storage devices 34 and are stored on the recording media (magnetic disks).
Further, during the transfer of the read data, the eight path data and the parity data read from the respective storage devices are temporarily stored in the register unit 45. Thereafter, these data are read into the read data converter 42, in which each CRC data is checked for each path by the device CRC checker 43, and the eight path data are converted into the four path data.
Thereafter, each CRC data is added to each of the four path data, which are transferred to the host computer after they are stored temporarily in the register unit 37.
In regard to the process of data check according to a prior art described above, there are the following problems.
(1) The data path control circuit 35 is provided with a large number of multiplexers, and therefore it is necessary for a complicated switching control of the multiplexers to be executed to switch paths for data conversion. At this time, the data may be erroneously transferred due to a failure of switching operations of some multiplexers. PA0 (2) For instance, the write data converter 40 and the read data converter 42 actually include a large number of multiplexers for executing such a switching control at high speed. Accordingly, if these devices fail during switching operations, a data error may occur. PA0 (3) In such a process of CRC checking, since the CRC data is added and checked for the data of each path separately, the above-mentioned data error, which may occur when the paths are erroneously changed with each other, cannot be detected.
In this case, for example, even if the paths #0 and #1 at the device side are erroneously changed with each other due to a failure of the switching operations, such a data error cannot be detected even when the CRC check is applied. Further, even if the same data as in the path #0 is output to the path #1 due to undesired switching operations, the error cannot be detected by the CRC check.
When these situations have occurred, erroneous data are transferred to the respective devices 34. Further, a user cannot notice that the data are erroneous, until the data are read from the devices 34 later and the CRC data check is executed for the read data. Consequently, the reliability of the data is deteriorated.